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Now lets talk about the future SRAM techniques. Many students in all universities and in many industries are concentrating on inventing something new in the memory area to make it even more compact and successful in performance wise. Everyday new techniques, tools, models and papers are emerging in every field. In a similar fashion there are lot more things going in most of the colleges and top notch companies in this field. Currently everyone are working in 22nm technology to achieve things in a more compact fashion. As discussed earlier everyone is worried about the wire delay and efficient approximate models for these and coupling effects are still in study. In SRAM it is highly expected to have a lot of changes in SRAM technology. Many new methods to improve the delay and performance will come up and many new testing methodology will emerge making SRAM even more compact and cheaper that expected. There is a high level expectation in the growth of this industry which may also produce many new intrusting products to market. This will also help in producing jobs. Hoping a lot more form this technology and from SRAM too. Read this and get some amount of knowledge on the memory which everyone using.

Errors and faults are prominent in any circuit. Correcting it is considered to be the difficult tasks. Worrying after the error as occurred after manufacturing process happens in all start up companies. Detail and throw checking of any design before sending it to manufacturing unit is considered to be very essential since we are spending almost over 60% money in creating the silicon chip. Success of any chip hence most truly lies in designers hand. Nowadays chip designers are clever because they are adding test pins and control logic while designing itself to correct the chip even after manufacturing is being done. Real physical properties as we all know is a probabilistic component and errors are unpredictable sometimes. Even though we design very carefully there may a possibility of going wrong while manufacturing. Out of experience it is seen that many times any one column in SRAM behaves in a different manner. Hence there is always a practice of adding redundant column during design phase. If in case test engineers report that this column is not functioning properly just feeding input to one pin transfers the control to the next column and the redundant column gets the control of column next to it. This method of correcting an error in a chip by just single I/p change is called steering since in this case we are steering all the column next to it. This method is proven to be very efficient.

Any test method is generally carried out by a random test vector. O/p’s for the given test vector is compared with the correct O/p to make sure that the circuit works properly. This type of technique is called signature analysis. But then just applying only one test vector doesn’t guarantee you that the circuit works properly on all conditions. At least we need to apply 40% of the I/p combination possible to be sure that the designed circuit works properly for almost all I/ps. Testing memory is some what similar to this. There are various methods to test the memories. March test is considered to be the most famous of all. There are various kinds of march test possible. Each and every scientist introduced different march test which guarantee the detection of some memory errors if present. Some of the common errors which can occur due to various defects and surrounding conditions are, when we write in one cell it gets written in the adjacent cells. Writing a one causes a write 0 or even 1 to the adjacent cell. Writing any value flips the value of the neighbors etc. some of the march test example march A and C+ are capable of finding almost all kinds of errors that can possibly occur in memory. Studies and researches are still going on to find an exact and efficient method of testing memories.

Different field which highly concerned about the logical verification and chip functionality in VLSI are test engineers. Job of every test engineer is of course a challenging since since they are about to test the chip which is been designed by some one. There are various methods of testing. Difference between testing and verification is that, testing is post manufacturing process and verification is pre-manufacturing process. Verification is done using various tools. Mainly functionality of the design under various corners are being verified. Only the design which passes the verification are send to factory for manufacturing. Testing, done after manufacturing is really a tough task since we may not know where the fault may have occurred. It is not possible to probe inside the circuits chips too. Various types of testing are stuck at fault, IDDQ, BIST, scan design for testability etc. among which stuck at fault test is most famous and it has capability of detecting all-most 90% of the faults. In-built testing is possible only when the circuit is designed with the test pins. Else separate probing is required which is the biggest head-ache. As and when the technology scales up testing becomes even more difficult since we are reducing the area drastically. From the survey it is seen that all the companies spend more time and money in testing rather that’s designing since that is considered to be the most important phase. With this introduction on testing lets see how memory testing is done.

Register files generally called as RF files are smaller version of SRAM which has considerably less no of cells in the cell array compared to the real SRAM. It is well known fact that as and when the no : of cells in SRAM increases it increases the overall capacitance that it has to undergo there by increasing the delay. That is write and read time are considerably poor as and when the no of cells increases in the cell array. In PC or in any OS there are certain instructions which are repeated again and again which needs quicker access for performance improvement of the process. It is very much applicable in multo-process environment which the present day OS deals with. These memories which provides faster access is said to be cache memory which plays an important role in computer architecture. Cache D1 D2 etc are different kings of cache which has various timing properties according to its memory capacity. Generally register files are nothing but cache memory which has been placed near processor chips. Nowadays cache memories are included inside the processor itself for faster access. Almost a glitch of various topics in SRAM is been covered till now except the testing part of it. We will see more about the memory testing in the future posts.

Till now we have been disusing the various parameters, design factors and timing details of SRAM. From the discussion it is been so clear that there are many no of ways in which we can design SRAM. Requirement will vary from company to company who uses the RAM in their chip. They will be like, i need this many address with this many rows and columns. I want decode 2 option with write and read performance of this much to suit my needs. Since there are lot of companies and they will ask different configuration obviously, its is difficult for a company to design such a lot of same SRAM design. Hence what companies now doing are, they are creating one common layout and schematic which suits all the design. And a scripting language to combine all this and give a complete SRAM. All the company people have to do is to specify their needs as inputs to the scripting language and run it. It will create the design according to the Inputs specified. This technique is called compiler design which is off great challenge and many companies like IBM has achieved it. Next we will see what is register files and how they are related to SRAM.

Timing details in any circuit is considered to be so important. Based on the delay parameters only designers can come to a conclusion wether they can introduce this product in market, is it better than products of other company etc. Time to market is also an important cause of making the product more successful. Similarly SRAM also has various timing’s like write time, read time, access time, cycle time etc. In general every circuit has rise time and fall time. It is defined as time taken to rise (or fall) from 0.1 to 0.9 Vdd ( 0.9 to 0.1 Vdd). Delay is generally measured in terms of time taken between I/p change from 50% which causes the same 50% change in O/p. When we consider Flip-flops and latches there is something called clock to q delay and D to q delay which has its own minimum and maximum delay problem. Read time is defined as time for the SA O/p to reach 50% of its value from the time the read enable signal reaches 50%. similarly write time is defined as time for the cell to write 50% of the value from the point the write enable goes to 50%. Access time is the time gap between 2 consecutive reads and writes. This time is usually greater than the read and write time. This clearly tells you the fact that as soon as you write or read a cell u need give some time for the BL lines to get pre-charged before starting any operation. Lastly cycle time is defined as the time for which one write and one read cycle gets completed. Cycle time determines the frequency at which the designed circuit can work.

Similar to write assist there is yet another circuit which is used to solve the problem of cells being flipped at extreme corners. This technique is being highly adopted by the design engineers when compared to write assist since it give more performance. Similar problem of reducing Vgs of the pass transistor is achieved differently by reducing the bit line voltages pulling it down to negative voltage instead of ground and ensuring perfect read stability. While write assist is for increasing the write stability, VBL regulation is for increasing the read stability. Even pre-charging of BLT and BLC lines are done to a level of 70 to 80% of Vcs where as Vcs is yet another supply voltage when compared to Vdd but it is very much less than Vdd. This generation of various voltages less than Vdd in-order to pre-charge the bit-lines are achieved with the help of voltage divider circuit. Moreover G-bias is an I/p to the Pmos which is connected to Vcs which is generated from the comparator circuit. VBL regulation is most useful method which gives performance benefit of up-to 10% but then it occupies lot of area due to complex circuitry. Coming post will explain you in brief about the SRAM timing.

One of the major problems which designers faced due to process variation is that, write time is not appreciable which affected the cycle time indirectly. This is because of the pass transistor which is not capable of passing a 1 being an nmos, at times when we do simulations at lower corners for 3 to 4 sigma variations then there was a possibility of cells flipping (stored 1 becomes 0 and stored 0 becomes 1). This is considered to be the most serious problem. Hence when SRAM operates at those corners there must be some circuitry which allows the cell to function properly. One way of achieving it is by increasing the Vgs (voltage across gate and source) of the nmos device by pulling the gate voltage applied to negative value. This assist the performance of write and make SRAM stable at all conditions. Hence this type of circuit which performs this assist action at lower corners is called write assist circuitry. Capacitor which actually sees positive charge is suddely made to see negative charge there by pulling the voltage across it to negative value to few mV which is being connected to the gate of that nmos. This is technique is proved to be more efficient in the present day technology. This may increase the area but for sure ensures the proper operation which is more important.